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Test Structures for Nano-Gap Fabrication Process Development for Nano-Electromechanical Systems

机译:纳米机电系统纳米间隙制造工艺开发的测试结构

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摘要

Nanometre scale pores, gaps or trenches are of significant interest for a number of applications in nano and microsystems, including biosensors, nanofluidic devices and mechanical resonators. This paper presents the design of two teststructure chips for the development of a process capable of the fabrication of controllable nanoscale trenches or gaps. This process uses uses standard microfabrication technologies, without the need for nano-scale lithography. Initial results from the first test chip have suggested design rules for pattern density and feature size for the process, which relies on chemical mechanical planarisation of polysilicon. These results have been used to inform the design of a second test chip which includes mechanical and electrical test structures. Initial results show that HF etch rate of a nanoscale silicon oxide used as a sacrificial layer can be very high, even for the very high aspect ratio features in this process.
机译:对于纳米和微系统中的许多应用,包括生物传感器,纳米流体装置和机械谐振器,纳米级的孔,间隙或沟槽引起了极大的兴趣。本文介绍了两种测试结构芯片的设计,以开发能够制造可控纳米级沟槽或间隙的工艺。该工艺使用标准的微加工技术,无需纳米级光刻。第一个测试芯片的初步结果为该工艺的图案密度和特征尺寸提出了设计规则,该规则取决于多晶硅的化学机械平面化。这些结果已用于告知包含机械和电气测试结构的第二测试芯片的设计。初步结果表明,即使在此工艺中具有非常高的长宽比特征,用作牺牲层的纳米级氧化硅的HF蚀刻速率也可能很高。

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